The advantage is not a faster chip. It is a way of running the chip you have so it computes where it used to only be measured — holding lock under drift, deciding before the deadline, and scaling to problem sizes a digital outer loop cannot reach. Below is what that is worth, built from third-party cost baselines and our measured performance, tiered honestly.
Every other method reads the wave plant’s output and then does its thinking in the digital substrate — estimate a gradient, fit a model, run a search, then write a configuration. SWC writes a direct residual from the measured output straight back to the writable control configuration, which evolves in place on the plant. The digital side is just the wire closing the loop. The update law is linear; coupled through the device’s interference each round, the trajectory converges on solutions that are nonlinear in the problem.
The settings of the plant evolve from the plant’s own response, not from state transitions in a digital optimizer. The outer loop stops being the speed limit.
One measurement becomes the next configuration directly. The per-round cost stays flat while the converged answer captures nonlinear structure a single linear step never could.
The retained-state convergence behaviour is established against fairly-tuned baselines. What remains is the wall-clock economics on physical hardware — the active next step.
Calibration is downtime: a quantum processor cannot run jobs while it recalibrates, and it drifts the moment it stops. This is the cleanest place to read the value, because the cost of that downtime is public and the runtime’s measurement-efficiency maps straight onto it — cheap continuous residual correction holds the setpoint instead of stopping to re-tune.
Baseline (sourced): IBM systems >7 qubits need 90 min/day + 2–3 min hourly calibration; tens-of-qubit systems reach up to 4 hrs/day of downtime (arXiv 2507.12323, 2407.18339). Cost (sourced): cloud QPU runtime lists at $48–$96 / min (IBM tiers, 2026). Multiplier (simulated): the runtime’s one-measurement-per-update efficiency recovers a fraction of that downtime by holding lock between full recals. recovered min/day × $/min × 250 days lands in the $0.6–1.4M/yr band per high-duty device. This is a projection, not booked savings, and assumes a high-utilization device where downtime displaces paid work.
This is the largest prize and the one the hardware pilot is built to prove. A photonic mesh held locked under thermal drift — and, for diagonal / QUBO-type objectives, driven by the mesh itself — turns a passive interferometer into a co-processor for continuous, deadline-bound optimization. On a thin-film lithium-niobate PIC at the edge, that is real-time optimization where a datacenter round-trip is impossible.
The runtime is the control layer, not the photonic interconnect, so we do not attach a hardware-market dollar figure to it — the honest lever is operational (fewer measurements, less downtime, tighter lock) and the capability story is the stronger one. The wall-clock “propagation speed” advantage depends on the optical-measurement-to-digital-evaluation ratio, which is hardware-dependent and not yet measured on a physical device. The algorithmic advantage (fewer rounds) is simulated and solid; the timing advantage is projected until the PIC pilot.
Phased-array ultrasound, optical inspection, GPR, RF front-ends — any loop where each measurement is expensive and the operating point drifts. The value is recovering a usable setting from few reads, so an instrument spends its budget on results instead of on re-tuning.
On-device AI at the edge needs continuous, heavy, deadline-bound optimization — the kind a cloud round-trip cannot serve. You will not put a quantum computer in a car, but you can put a thin-film lithium-niobate PIC running SWC beside the AI as the co-processor that handles exactly that load. As the world’s problems grow, so does the problem size; a loop that converges on the device instead of stalling in a digital outer loop is how the hardware keeps up. The evidence so far backs the mechanism. The hardware step is what turns it into the economics above.
Every dollar figure on this page is a projection: a third-party cost baseline (cited inline) multiplied by a performance multiplier established in controlled simulation against fairly-tuned baselines. They are not booked savings, and they assume the hardware-validation step — which witnesses the retention mechanism, not a rate claim — lands as the simulation predicts.
Where a causal chain to dollars is weak (photonic / edge), we say so and lead with capability instead. Sourcing: arXiv 2507.12323, 2407.18339, 2411.19308 (quantum calibration overhead & downtime); IBM Quantum / AWS Braket public rate cards, 2026 (QPU runtime cost); dataintelo / Technavio (photonic market backdrop). The runtime’s own results are detailed on the homepage and compatibility page.